The present disclosure relates generally to the manufacturing of semiconductor devices, and more particularly to a system and method for overlay measurement in semiconductor manufacturing.
The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller feature sizes and more complex circuits than those from the previous generation.
Currently, semiconductor devices are fabricated by patterning a sequence of patterned and un-patterned layers, and the features on successive patterned layers are spatially related to each another. During the fabrication, each patterned layer must be aligned with the previous patterned layers with a degree of precision. Therefore, pattern recognition is a key part of successful photolithography.
Conventional pattern recognition is done by a pattern alignment technique. A lower (previous) patterned layer will include an overlay target, and a second pattern on an upper (next) patterned layer can then be aligned. However, this alignment technique can provide difficulties in recognizing the overlay target, especially in fabrication techniques such as damascene or dual damascene. Techniques other than damascene or dual damascene processes also experience such difficulties.